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Tips for Enhancing ESD Protection Application Note
Board designers must ensure the external ESD (electrostatic discharge) protection they select is robust enough to protect today’s small geometry chipsets. All too often, the ESD device does not provide enough protection by itself, leading to a premature failure of the chipset.
This application note offers guidelines that designers can use to enhance on-board ESD protection.
Readers will learn about:
- The impact of parasitic inductances when determining appropriate device placement and layout
- Four strategies board designers can use to optimize their ESD solutions
- The use of buffering resistors between the ESD suppression device and the chipset being protected
